1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which multiple external connection electrodes can be arranged.
2. Description of the Related Art
There conventionally exists a so-called CSP (Chip Size Package) semiconductor device. The CSP is constructed on a semiconductor substrate on which a plurality of connection pads are formed, and wires are laid on the connection pads via an insulation film so as to be connected to the connection pads. Columnar electrodes are formed on the connection pad portions of the wires and a sealing film is formed on the wires and the insulation film in a manner that the top surface of the sealing film constitutes the same surface as the top surfaces of the columnar electrodes (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2000-22052, FIG. 8).
There is another type of conventional semiconductor device which has solder balls as external connection terminals outside the range of the semiconductor substrate included in the device. In this device, a semiconductor substrate having a plurality of connection pads thereon is formed on a base plate, and an insulation layer is formed on the base plate portion that appears around the semiconductor substrate. An upper insulation film is formed on the semiconductor substrate and the insulation layer, and upper wires are provided on the upper insulation film so as to be connected to the connection pads on the semiconductor substrate. The portions other than the connection pad portions of the upper wires are covered with an overcoat film, and solder balls are formed on the connection pad portions of the upper wires (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2003-298005).
It is now possible that the semiconductor device disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2000-22052 (the semiconductor device will hereinafter be referred to as semiconductor element) having the columnar electrodes be formed on the base plate disclosed in the Unexamined Japanese Patent Application KOKAI Publication No. 2003-298005 instead of the semiconductor substrate disclosed therein. To be more specific, it is possible that the semiconductor element having the columnar electrodes be formed on the base plate, an insulation layer be formed on the base plate portion that appears around the semiconductor element, an upper insulation film be formed on the semiconductor element and the insulation layer, upper wires are provided on the upper insulation film so as to be connected to the columnar electrodes of the semiconductor element, the portions other than the connection pad portions of the upper wires be covered with an overcoat film, and solder balls be formed on the connection pad portions of the upper wires.
In a case where the diameter of the columnar electrode is 120 μm, the state-of-the-art manufacture techniques tolerate about 200 μm as the limit of the arranging pitch for the columnar electrodes, and about 70 μm as the limit of the arranging pitch for the upper wires (wire width being about 35 μm and wire interval being about 35 μm). In this case, the interval between the columnar electrodes having the diameter of 120 μm and arranged with the arranging pitch of 200 μm is 80 μm, and therefore the number of upper wires having the wire width of 35 μm that can be arranged on the upper insulation film within the interval of 80 μm is 1.
If the largest number of columnar electrodes possible under the above-described conditions are arranged on the circumferential region of a semiconductor substrate having the size of 5 mm×5 mm, the semiconductor substrate will be as shown in FIG. 19. That is, in a case where a semiconductor substrate 41 is a square each side of which has a length of 5 mm and columnar electrodes 42 having a diameter of 120 μm are arranged along each side with an arranging pitch of 200 μm, the number of columnar electrodes 42 is 24 according to a calculation “(5000÷200)−1=24” and the total number thereof along the four sides is 92 according to a calculation “(24−1)×4=92”. That is, the total number of columnar electrodes 42 that are arranged for the first round along the four sides of the semiconductor substrate 41 is 92.
Further, since upper wires 44 can be arranged on the upper insulation film 43 within the intervals between the respective 92 columnar electrodes 42 arranged along the four sides on the basis of one wire for each interval as shown in FIG. 20, further columnar electrodes 42 can be arranged inside and along the 92 columnar electrodes 42 arranged along the four sides as shown in FIG. 19. In this case, the number of the second round of columnar electrodes 42 arranged along the first round of columnar electrodes 42 is 22 per side, smaller by 2 than the number of columnar electrode 42 arranged outside (first round). That is, the total number of the second round of columnar electrodes 42 arranged along the four sides of the semiconductor substrate 41 is 84 according to a calculation “(22−1)×4=84”. Further, since there occur 8 intervals in which no wire is arranged between the columnar electrodes 42 as shown in FIG. 20 when the columnar electrodes 42 are arranged two rounds as described above, 8 more columnar electrodes 42 can be arranged for the third round inside the 84 columnar electrodes 42 arranged for the second round. As a result, in the conventional structure in which the columnar electrodes 42 are arranged as shown in FIG. 19 and FIG. 20, the total number of columnar electrodes 42 is 184 according to a calculation “(92+84+8)=184”.